A fundamental shift is taking place in the fabrication of integrated circuits, and in particular in the construction of the multiple wiring layers that provide connections to the tens of millions of transistors on a state-of-the-art chip. For decades, the standard in the industry has been the use of aluminum wires isolated from each other by silicon dioxide. Despite the success of this combination, it is now placing limitations on the performance of the chips. In order to obviate these limitations, the semiconductor industry has begun to search for replacements for aluminum and/or silicon dioxide that can provide enhanced device performance.
Two shifts in fabrication of integrated circuits are currently taking place: (1) from aluminum to copper wires to reduce the resistance of the metal wires, and (2) from silicon dioxide to dielectrics with lower dielectric constants k, commonly referred to as ‘low-k’ materials. The move away from silicon dioxide as the interlayer dielectric has been driven by the need to reduce the delay times along the wires in the complex circuits. This has opened up a wide field of research and development in the semiconductor industry focused on the fabrication and characterization of new high-performance materials.
However, the stable, well-understood nature of silicon dioxide has led to an absence of effective tools and methods for characterizing dielectric materials. As a result, progress toward the identification and optimization of new dielectric materials is slowed by the lack of characterization instruments.
In standard aluminum/silicon dioxide processes, the wiring layers are formed by first laying down a uniform aluminum film, etching away the aluminum in the regions between the wires, and then filling these regions with silicon dioxide. The switch from aluminum to copper has changed this process, since there is no effective way to etch copper. Thus, for copper/dielectric based integrated circuits, the Damascene process is generally used, in which the dielectric material (either silicon dioxide or a low-k dielectric) is initially deposited. The dielectric layer is then etched to form trenches where the wires will be formed and finally the copper is deposited into these trenches.
The Damascene process has been somewhat successful, but has also led to a wide range of problems that were not encountered in the standard Al/SiO2 technology. These problems have been particularly common when the typically less-stable low-k dielectrics are used. For example, the dielectric etching process necessary to form the trenches for copper often damage the dielectric material causing a change in its dielectric constant, and as a consequence, a change in the performance of the device. This type of damage often occurs at the interface between the metal and dielectric and causes changes in the capacitance between wires, thus affecting device performance.
Measuring capacitance is an important step in monitoring the fabrication process of integrated circuits. The standard method for doing this is to build large capacitance test structures directly into the device itself and then measure the capacitance of these structures by making direct contact to them either through pins on the finished device or by placing small probes on contact pads. This type of measurement is typically limited to relatively low frequencies (below 1 MHz) and requires large test structures in order to have a large enough capacitance (>1 pico Farad) to overcome the stray capacitances in the system.
It therefore would be highly desirable to have a non-contact technique for capacitance measurement of miniature structures performed at microwave (and higher) frequencies.